Principal Product Engineer

Principal Product Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Principal Product Engineer

Grade: T4

Experience: 7-12 Years

Location: Bangalore/Noida

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.

• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success

• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

• We offer amazing opportunities to grow, no matter where you are in your career.

Job responsibilities:

• This opportunity is for a Principal Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms.

Experience and Technical Skills required:

• Main function is to perform PPA improvement on critical customer designs Good knowledge of physical design flow from netlist to gdsii including, floorplanng, power planning, placement, CTS, and routing.

• Good understanding of timing concepts.

• Candidates should have excellent debugging skills and understanding of timing, congestion, power optimization, routing, drcs etc.

• Should have worked on low technology nodes 5nm and below (at least 7nm).

• Experience with 3nm or 2nm technologies would be a plus.

• Should be able to manage benchmarks and communicate with the customer on the issues and progress of the activity.

• Multi tasking on different issues and with different teams is required.

• Working with Research and Development (R&D) to discuss results and next steps for Innovus' features

Qualifications

• BE/BTech/ME/MS/MTech or equivalent

We’re doing work that matters. Help us solve what others can’t.

Experience Level

Senior Level